Non-volatile memory with atonomous cycling

ABSTRACT

A memory die assembly, comprising a non-volatile memory structure, performs autonomous testing of the memory die assembly by repeatedly performing a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure. Failure events from the tests are recorded by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event, a type of test that failed and a cycle during which the failure event occurred.

BACKGROUND

The present disclosure relates to non-volatile storage.

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND-type and NOR-type flash memory).

Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory. Later, a user of the digital camera may view the photograph by having the digital camera read the photograph from the non-volatile memory. Because users often rely on the data they store, it is important to users of non-volatile memory to be able to store data reliably so that the data can be read back successfully.

In order to insure that non-volatile memory stores data reliably, non-volatile memory is tested during the development phase and during the manufacturing phase. For example, during the development phase engineers test the design to make sure that operation of the designed memory is reliable over various conditions and usage. At the time of fabrication, manufacturers screen for fabrication defects (e.g., wafer level burn in and package level bum in). For both testing during the development phase and testing during the manufacturing phase, a memory die is connected to an integrated circuit tester (that is separate from the memory die), which is connected to and controlled by a personal computer (or other processor). The testing is performed by the personal computer exchanging commands and responses with the integrated circuit tester, the integrated circuit tester formulating tests, the integrated circuit tester exchanging commands and responses with the memory die, and the memory die performing tests under the control of the integrated circuit tester. The testing typically comprises running a group of tests multiple times, where each time the group of tests is run is referred to as a cycle. For example, a memory die can be tested for 10-100,000 cycles, or more.

The testing of the memory die for many cycles is time consuming. During the development phase, the testing of the memory die for many cycles slows down the development cycle. During the manufacturing phase, the testing of the memory die for many cycles slows down the manufacturing process, which delays sales and the recouping of investment.

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the different figures.

FIG. 1 is a block diagram depicting one embodiment of a storage system.

FIG. 2A is a block diagram of one embodiment of a memory die.

FIG. 2B is a block diagram of one embodiment of an integrated memory assembly.

FIGS. 2C and 2D depict different embodiments of integrated memory assemblies.

FIG. 3 depicts circuitry used to sense data from non-volatile memory.

FIG. 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

FIG. 4A is a block diagram of one embodiment of a memory structure having four planes.

FIG. 4A1 is a block diagram of a portion of the control circuit positioned under a plane of non-volatile memory cells.

FIG. 4A2 depicts a set of latches.

FIG. 4B depicts a top view of a portion of one embodiment of a block of memory cells.

FIG. 4C depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4D depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4E depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4F is a cross sectional view of one embodiment of a vertical column of memory cells.

FIG. 4G is a schematic of a plurality of NAND strings in multiple sub-blocks of a same block.

FIG. 5A depicts threshold voltage distributions.

FIG. 5B depicts threshold voltage distributions.

FIG. 5C depicts threshold voltage distributions.

FIG. 5D depicts threshold voltage distributions.

FIG. 6 is a flow chart describing one embodiment of a process for programming non-volatile memory.

FIG. 7 is a block diagram depicting the testing of a memory die assembly.

FIG. 8 is a flow chart describing one embodiment of a process for autonomous testing of a memory die assembly.

FIG. 9 is a flow chart describing one embodiment of a process for autonomous testing of a memory die assembly.

FIG. 10 is a block diagram depicting the ganging of blocks and saving of error data from the autonomous testing of a memory die assembly.

FIG. 11 is a table describing where error data is stored during the autonomous testing of a memory die assembly.

FIG. 12 is a table depicting one embodiment of a format for a record that stores error data for one failure event during the autonomous testing of a memory die assembly.

FIG. 13 is a block diagram depicting how the records of FIG. 12 are stored in non-volatile memory.

FIGS. 14A, 14B and 14C together form a flow chart that describes an embodiment of a process for autonomous testing of a memory die assembly.

FIGS. 15A1 and 15A2 together with FIGS. 14B and 14C form a flow chart that describes another embodiment of a process for autonomous testing of a memory die assembly.

DETAILED DESCRIPTION

It has been determined that a large portion of the time need to test a memory die, during the development phase or the manufacturing phase, is used for: (1) communicating between the personal computer, integrated circuit tester and memory die, and (2) the integrated circuit tester managing the test process. Therefore, a memory die assembly, comprising a non-volatile memory structure, is proposed that performs autonomous testing of the memory die assembly by repeatedly performing a group of tests for multiple cycles. The autonomous testing is performed in response to a request from an entity external to the memory die assembly (e.g., an integrated circuit tester), and is accomplished without being managed by the entity external to the memory die assembly. Because the communication and data transfer between the memory die assembly and the entity external to the memory die assembly is reduced, the time needed for testing is also significantly reduced.

FIG. 1 is a block diagram of one embodiment of a storage system 100 that implements the proposed technology described herein. In one embodiment, storage system 100 is a solid state drive (“SSD”). Storage system 100 can also be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Storage system 100 is connected to host 102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from, but connected to, storage system 100. In other embodiments, storage system 100 is embedded within host 102.

The components of storage system 100 depicted in FIG. 1 are electrical circuits. Storage system 100 includes a memory controller 120 connected to non-volatile memory 130 and local high speed volatile memory 140 (e.g., DRAM). Local high speed volatile memory 140 is used by memory controller 120 to perform certain functions. For example, local high speed volatile memory 140 stores logical to physical address translation tables (“L2P tables”).

Memory controller 120 comprises a host interface 152 that is connected to and in communication with host 102. In one embodiment, host interface 152 implements a NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. NOC’s can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 can be replaced by a bus. Connected to and in communication with NOC 154 is processor 156, ECC engine 158, memory interface 160, and DRAM controller 164. DRAM controller 164 is used to operate and communicate with local high speed volatile memory 140 (e.g., DRAM). In other embodiments, local high speed volatile memory 140 can be SRAM or another type of volatile memory.

ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 158 is an electrical circuit programmed by software. For example, ECC engine 158 can be a processor that can be programmed. In other embodiments, ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 158 is implemented by processor 156.

Processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. Processor 156 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller 120 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain tables (i.e. the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory 140 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die 130 and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory 140.

Memory interface 160 communicates with non-volatile memory 130. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface 160 (or another portion of controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.

In one embodiment, non-volatile memory 130 comprises one or more memory die. FIG. 2A is a functional block diagram of one embodiment of a memory die 200 that comprises non-volatile memory 130. Each of the one or more memory die of non-volatile memory 130 can be implemented as memory die 200 of FIG. 2A. The components depicted in FIG. 2A are electrical circuits. Memory die 200 includes a memory array 202 that can comprises non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented. Memory die 200 includes row control circuitry 220, whose outputs 208 are connected to respective word lines of the memory array 202. Row control circuitry 220 receives a group of M row address signals and one or more various control signals from System Control Logic circuit(s) 260, and typically may include such circuits as row decoders 222, array terminal drivers 224, and block select circuitry 226 for both reading and writing (programming) operations. Row control circuitry 220 may also include read/write circuitry. Memory die 200 also includes column control circuitry 210 including sense amplifier(s) 230 whose input/outputs 206 are connected to respective bit lines of the memory array 202. Although only single block is shown for array 202, a memory die can include multiple arrays that can be individually accessed. Column control circuitry 210 receives a group of N column address signals and one or more various control signals from System Control Logic 260, and typically may include such circuits as column decoders 212, array terminal receivers or driver circuits 214, block select circuitry 216, as well as read/write circuitry, and I/O multiplexers.

System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which comprises one or more electrical circuits) include state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 262 is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic 262 can also include a power control module 264 that controls the power and voltages supplied to the rows and columns of the memory structure 202 during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic 262 includes storage 266 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory array 202.

Commands and data are transferred between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as a “communication interface”). Memory controller interface 268 is an electrical interface for communicating with memory controller 120. Examples of memory controller interface 268 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used.

In some embodiments, system control logic 262 can also includes Autonomous Cycling Module (ACM) circuit 269, which is used to perform autonomous testing of memory array 202 (or other memory structure) using a group of tests multiple times, where each time the group of tests is run is referred to as a cycle. More details of ACM 269 are provided below.

In some embodiments, all the elements of memory die 200, including the system control logic 260, can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on a different die.

In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers.

In another embodiment, memory structure 302 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer’s magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.

Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe - Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or noncontinuous) vibration or burst of sound, current, voltage light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

The elements of FIG. 2A can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes all of the other components depicted in FIG. 2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of storage system 100 that is given over to the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic 260, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system 100 is the amount of area to devote to the memory structure 202 and the amount of area to devote to the peripheral circuitry.

Another area in which the memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.

To improve upon these limitations, embodiments described below can separate the elements of FIG. 2A onto separately formed dies that are then bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more die, such as two memory die and one control die, for example.

FIG. 2B shows an alternative arrangement to that of FIG. 2A which may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement the non-volatile memory 130 of storage system 100. The integrated memory assembly 207 includes two types of semiconductor die (or more succinctly, “die”). Memory die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

FIG. 2B shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die 211 coupled to memory structure 202 formed in memory die 201. Common components are labelled similarly to FIG. 2A. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on the memory die 201. In some embodiments, some of the circuitry in the system control logic 260 is located on the on the memory die 201.

System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while moving such circuits from a die such as memory 2 die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 211 may not require many additional process steps. The control die 211 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.

FIG. 2B shows column control circuitry 210 including sense amplifier(s) 230 on the control die 211 coupled to memory structure 202 on the memory die 201 through electrical paths 206. For example, electrical paths 206 may provide electrical connection between column decoder 212, driver circuitry 214, and block select 216 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of the memory die 201, which are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical paths 206, including a pair of bond pads, which connects to column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, array drivers 224, and block select 226 are coupled to memory structure 202 through electrical paths 208. Each of electrical path 208 may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die 211 and memory die 201.

For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and/or other similar functioned circuits. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

In some embodiments, there is more than one control die 211 and more than one memory die 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control die 211 and multiple memory die 201. FIG. 2C depicts a side view of an embodiment of an integrated memory assembly 207 stacked on a substrate 271 (e.g., a stack comprising control dies 211 and memory dies 201). The integrated memory assembly 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control die 211.

Each control die 211 is affixed (e.g., bonded) to at least one of the memory dies 201. Some of the bond pads 282/284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as solid layer 280, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

The integrated memory assembly 207 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. A number of such wire bonds may be formed across the width of each control die 211 (i.e., into the page of FIG. 2C).

A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211. The TSVs 276, 278 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 201, 211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package. The solder balls 272 may form a part of the interface between integrated memory assembly 207 and memory controller 120.

FIG. 2D depicts a side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271. The integrated memory assembly 206 of FIG. 2D has three control die 211 and three memory die 201. In some embodiments, there are many more than three memory dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 may be bonded to two or more memory die 201.

Some of the bond pads 282, 284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the example in FIG. 2C, the integrated memory assembly 207 in FIG. 2D does not have a stepped offset. A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package.

As has been briefly discussed above, the control die 211 and the memory die 201 may be bonded together. Bond pads on each die 201, 211 may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 µm square and spaced from each other with a pitch of 5 µm to 5 µm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.

When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 µm square and spaced from each other with a pitch of 1 µm to 5 µm. Bonding techniques may be used providing bond pads with even smaller (or greater) sizes and pitches.

Some embodiments may include a film on surface of the dies 201, 211. Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

FIG. 3 is a block diagram depicting one embodiment of a portion of column control circuitry 210 that is partitioned into a plurality of sense amplifiers 230, and a common portion, referred to as a managing circuit 302. In one embodiment, each sense amplifier 230 is connected to a respective bit line which in turn is connected to one or more NAND strings. In one example implementation, each bit line is connected to six NAND strings, with one NAND string per sub-block. Managing circuit 302 is connected to a set of multiple (e.g., four, eight, etc.) sense amplifiers 230. Each of the sense amplifiers 230 in a group communicates with the associated managing circuit via data bus 304.

Each sense amplifier 230 operates to provide voltages to bit lines (see BL0, BL1. BL2. BL3) during program, verify, erase and read operations. Sense amplifiers are also used to sense the condition (e.g., data state) to a memory cells in a NAND string connected to the bit line that connects to the respective sense amplifier.

Each sense amplifier 230 includes a selector 306 or switch connected to a transistor 308 (e.g., an nMOS). Based on voltages at the control gate 310 and drain 312 of the transistor 308, the transistor can operate as a pass gate or as a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to pass the voltage at the drain to the bit line (BL) at the source 314 of the transistor. For example, a program-inhibit voltage such as 1-2 V may be passed when pre-charging and inhibiting an unselected NAND string. Or, a program-enable voltage such as 0 V may be passed to allow programming in a selected NAND string. The selector 306 may pass a power supply voltage Vdd, (e.g., 3-4 V) to the control gate of the transistor 308 to cause it to operate as a pass gate.

When the voltage at the control gate is lower than the voltage on the drain, the transistor 308 operates as a source-follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage on the control gate 310 and Vth, e.g., 0.7 V, is the threshold voltage of the transistor 308. This assumes the source line is at 0 V. If Vcelsrc is non-zero, the bit line voltage is clamped at Vcg-Vcelsrc-Vth. The transistor is therefore sometimes referred to as a bit line clamp (BLC) transistor, and the voltage Vcg on the control gate 310 is referred to as a bit line clamp voltage, Vblc. This mode can be used during sensing operations such as read and verify operations. The bit line voltage is thus set by the transistor 308 based on the voltage output by the selector 306. For example, the selector 306 may pass Vsense+Vth, e.g., 1.5 V, to the control gate of the transistor 308 to provide Vsense, e.g., 0.8 V, on the bit line. A Vbl selector 316 may pass a relatively high voltage such as Vdd to the drain 312, which is higher than the control gate voltage on the transistor 308, to provide the source-follower mode during sensing operations. Vbl refers to the bit line voltage.

The Vbl selector 316 can pass one of a number of voltage signals. For example, the Vbl selector can pass a program-inhibit voltage signal which increases from an initial voltage, e.g., 0 V, to a program inhibit voltage, e.g., Vbl_inh for respective bit lines of unselected NAND string during a program loop. The Vbl selector 316 can pass a program-enable voltage signal such as 0 V for respective bit lines of selected NAND strings during a program loop.

In one approach, the selector 306 of each sense circuit can be controlled separately from the selectors of other sense circuits. The Vbl selector 316 of each sense circuit can also be controlled separately from the Vbl selectors of other sense circuits.

During sensing, a sense node 318 is charged up to an initial voltage, Vsense_init, such as 3 volts. The sense node is then passed to the bit line via the transistor 308, and an amount of decay of the sense node is used to determine whether a memory cell is in a conductive or non-conductive state. The amount of decay of the sense node also indicates whether a current Icell in the memory cell exceeds a reference current, Iref. A larger decay corresponds to a larger current. If Icell<=Iref, the memory cell is in a non-conductive state and if Icell>Iref, the memory cell is in a conductive state.

In particular, the comparison circuit 320 determines the amount of decay by comparing the sense node voltage to a trip voltage at a sense time. If the sense node voltage decays below the trip voltage, Vtrip, the memory cell is in a conductive state and its Vth is at or below the verify voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is above the verify voltage. A sense node latch 322 is set to 0 or 1, for example, by the comparison circuit 320 based on whether the memory cell is in a conductive or non-conductive state, respectively. For example, in a program-verify test, a 0 can denote fail and a 1 can denote pass. The bit in the sense node latch can be read out in a state bit scan operation of a scan operation or flipped from 0 to 1 in a fill operation. The bit in the sense node latch 322 can also be used in a lockout scan to decide whether to set a bit line voltage to an inhibit or program level in a next program loop.

Managing circuit 302 comprises a processor 330, four example sets of data latches 340, 342, 344 and 346, and an I/O interface 332 coupled between the sets of data latches and the data bus 334. FIG. 3 shows four example sets of data latches 340, 342, 344 and 346; however, in other embodiments more or less than four can be implemented. In one embodiment, there is one set of latches for each sense amplifier 230. One set of five data latches, e.g., comprising individual latches ADL, BDL, CDL, TDL and XDL, can be provided for each sense circuit. In some cases, a different number of data latches may be used. In a three bit per memory cell embodiment, ADL stores a bit for a lower page of data, BDL stores a bit for a middle page of data, CDL stores a bit for an upper page of data and XDL typically serves as an interface latch for storing/latching data from the memory controller. TDL can be used to store a last comparison of an even result to an odd result, as described below.

Processor 330 performs computations, such as to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. Each set of data latches 340-346 is used to store data bits determined by processor 330 during a read operation, and to store data bits imported from the data bus 334 during a program operation which represent write data meant to be programmed into the memory. I/O interface 332 provides an interface between data latches 340-346 and the data bus 334.

During reading, the operation of the system is under the control of state machine 262 that controls the supply of different control gate voltages to the addressed memory cell. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit may trip at one of these voltages and a corresponding output will be provided from the sense amplifier to processor 330 via the data bus 304. At that point, processor 330 determines the resultant memory state by consideration of the tripping event(s) of the sense circuit and the information about the applied control gate voltage from the state machine via input lines 348. It then computes a binary encoding for the memory state and stores the resultant data bits into data latches 340-346.

Some implementations can include multiple processors 330. In one embodiment, each processor 330 will include an output line (not depicted) such that each of the output lines is connected in a wired-OR connection. A wired OR connection or line can be provided by connecting multiple wires together at a node, where each wire carries a high or low input signal from a respective processor, and an output of the node is high if any of the input signals is high. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during a program verify test of when the programming process has completed because the state machine receiving the wired-OR can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted). When all bits output a data 0 (or a data one inverted), then the state machine knows to terminate the programming process. Because each processor communicates with eight sense circuits, the state machine needs to read the wired-OR line eight times, or logic is added to processor 330 to accumulate the results of the associated bit lines such that the state machine need only read the wired-OR line one time. Similarly, by choosing the logic levels correctly, the global state machine can detect when the first bit changes its state and change the algorithms accordingly.

During program or verify operations for memory cells, the data to be programmed (write data) is stored in the set of data latches 340-346 from the data bus 334. During reprogramming, a respective set of data latches of a memory cell can store data indicating when to enable the memory cell for reprogramming based on the program pulse magnitude.

The program operation, under the control of the state machine 262, applies a series of programming voltage pulses to the control gates of the addressed memory cells. Each voltage pulse may be stepped up in magnitude from a previous program pulse by a step size in a processed referred to as incremental step pulse programming. Each program voltage is followed by a verify operation to determine if the memory cells has been programmed to the desired memory state. In some cases, processor 330 monitors the read back memory state relative to the desired memory state. When the two are in agreement, processor 330 sets the bit line in a program inhibit mode such as by updating its latches. This inhibits the memory cell coupled to the bit line from further programming even if additional program pulses are applied to its control gate.

FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure 202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example, FIG. 4 shows a portion 400 of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack 401 of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment the alternating dielectric layers and conductive layers are divided into four or five (or a different number of) regions (also referred to as sub-blocks) by isolation regions IR. FIG. 4 shows one isolation region IR separating two sub-blocks. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 4 , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory array that comprises memory structure 202 is provided below.

FIG. 4A is a block diagram explaining one example organization of memory structure 202, which is divided into four planes Plane 0, Plane 1, Plane 2 and Plane 3 (all positioned on the same die). Each plane is then divided into blocks. In one example, each plane has 915 - 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, blocks can be divided into sub-blocks and the sub-blocks can be the unit of erase. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells (e.g., NAND strings) as the memory cells of a block share a common set of word lines and bit lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block.

FIG. 4A1 is a block diagram of a portion 401 of the control circuits positioned under each plane of non-volatile memory cells. In a system that has four planes, four instances of the circuit 401 are includes with one instance of circuit 401 under each plane. In the embodiment of FIG. 2A, circuit 401 is positioned on the substrate of memory die 200, underneath memory array 202. In the embodiment of FIG. 2B, circuit 401 is positioned on the substrate of control die 211, underneath memory array 202 of memory die 201. Circuit 401 includes row decoders RD 401 on the sides of circuit 401. Row decoders RD 401 implement all or a portion of row control circuitry 220. Between row decoders RD 401 are control circuits for column 403, sense amplifiers with internal data latches 404 and cache buffer 505. Control circuits for column 403 implement a portion of column control circuitry 201 for the memory cells of the plane that circuit 401 is underneath and associated with. Sense amplifiers with internal data latches 404 implement a subset of the sense amplifiers 230 and a subset of the data latches (e.g., 340, 342, 344, 346) used with the memory cells of the plane that circuit 401 is underneath and associated with. In one embodiment, cache buffer 405 is volatile memory (e.g., SRAM or DRAM) that typically serves as a buffer and temporary storage for data going to the memory cells of the plane that circuit 401 is underneath and associated with and/or data read from the memory cells of the plane that circuit 401 is underneath and associated with.

In one embodiment, a first subset of the data latches (e.g., 340, 342, 344, 346 of FIG. 3 ) are implemented as part of sense amplifiers with internal data latches 404 and a second subset of the data latches are implemented as part of cache buffer 405. For example, FIG. 4A2 depicts a set of latches 340 such that a first subset of the data latches (e.g., ADL, BDL, CDL and TDL) are implemented as part of sense amplifiers with internal data latches 404 and a second subset of the data latches (e.g., XDL) are implemented as part of cache buffer 405. Other arrangements can also be used.

FIGS. 4B-4G depict an example three dimensional (“3D”) NAND structure that corresponds to the structure of FIG. 4 and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4B is a block diagram depicting a top view of a portion 406 of Block 2 of plane 402. As can be seen from FIG. 4B, the block depicted in FIG. 4B extends in the direction of 432. In one embodiment, the memory array has many layers; however, FIG. 4B only shows the top layer.

FIG. 4B depicts a plurality of circles that represent the vertical columns, which correspond to the memory holes. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example, FIG. 4B labels a subset of the vertical columns/NAND strings 432, 436, 446. 456, 462, 466, 472, 474 and 476.

FIG. 4B also depicts a set of bit lines 415, including bit lines 411, 412, 413, 414, ... 419. FIG. 4B shows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. For example, bit line 411 is connected to vertical columns 436, 446, 456, 466 and 476.

The block depicted in FIG. 4B includes a set of isolation regions 482, 484, 486 and 488, which are formed of SiO₂; however, other dielectric materials can also be used. Isolation regions 482, 484, 486 and 488 serve to divide the top layers of the block into five regions; for example, the top layer depicted in FIG. 4B is divided into regions 430, 440, 450, 460 and 470 all of which are referred to as sub-blocks. In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different sub-blocks can be independently selected. In one example implementation, a bit line connects to one vertical column/NAND string in each of regions (sub-blocks) 430, 440, 450, 460 and 470. In that implementation, each block has twenty four rows of active columns and each bit line connects to five rows in each block. In one embodiment, all of the five vertical columns/NAND strings connected to a common bit line are connected to the same set of word lines; therefore, the system uses the drain side selection lines to choose one (or another subset) of the five to be subjected to a memory operation (program, verify, read, and/or erase).

FIG. 4B also shows Line Interconnects LI, which are metal connections to the source line SL from above the memory array. Line Interconnects LI are positioned adjacent regions 430 and 470.

Although FIG. 4B shows each region 430, 440, 450, 460 and 470 having four rows of vertical columns, five regions and twenty four rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block. FIG. 4B also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

FIG. 4C depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line AA of FIG. 4B. This cross sectional view cuts through vertical columns (NAND strings) 472 and 474 of region 470 (see FIG. 4B). The structure of FIG. 4C includes three drain side select layers SGD0, SGD1 and SGD2; three source side select layers SGS0, SGS1, and SGS2; three dummy word line layers DD0, DD1, and DDS; two hundred and forty word line layers WL0-WL239 for connecting to data memory cells, and two hundred and fifty dielectric layers DL0-DL249. Other embodiments can implement more or less than the numbers described above for FIG. 4C. In one embodiment, SGD0, SGD1 and SGD2 are connected together; and SGS0, SGS1 and SGS2 are connected together. In other embodiments, more or less number of SGDs (greater or lesser than three) are connected together, and more or less number of SGSs (greater or lesser than three) connected together.

Vertical columns 472 and 474 are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each vertical column comprises a vertical NAND string. Below the vertical columns and the layers listed below is substrate 453, an insulating film 454 on the substrate, and source line SL. The NAND string of vertical column 442 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with FIG. 4B, FIG. 4C show vertical column 472 connected to bit line 414 via connector 417.

For ease of reference, drain side select layers; source side select layers, dummy word line layers and data word line layers collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten, metal silicide, such as nickel silicide, tungsten silicide, aluminum silicide or the combination thereof. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL0-DL249. For example, dielectric layers DL240 is above word line layer WL235 and below word line layer WL236. In one embodiment, the dielectric layers are made from SiO₂. In other embodiments, other dielectric materials can be used to form the dielectric layers.

The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0-W239 connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1 and DS connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect NAND strings from the source line SL.

FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line BB of FIG. 4B. This cross sectional view cuts through vertical columns (NAND strings) 432 and 434 of region 430 (see FIG. 4B). FIG. 4D shows the same alternating conductive and dielectric layers as FIG. 4C. FIG. 4D also shows isolation region 482. Isolation regions 482, 484, 486 and 488) occupy space that would have been used for a portion of the memory holes/vertical columns/NAND stings. For example, isolation region 482 occupies space that would have been used for a portion of vertical column 434. More specifically, a portion (e.g., half the diameter) of vertical column 434 has been removed in layers SDG0, SGD1, SGD2, and DD0 to accommodate isolation region 482. Thus, while most of the vertical column 434 is cylindrical (with a circular cross section), the portion of vertical column 434 in layers SDG0, SGD1, SGD2, and DD0 has a semi-circular cross section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region and that space is then filled in with SiO₂.

FIG. 4E depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line CC of FIG. 4B. This cross sectional view cuts through vertical columns (NAND strings) 452 and 4624 (see FIG. 4B). FIG. 4E shows the same alternating conductive and dielectric layers as FIG. 4C. FIG. 4E also shows isolation region 486 cutting into vertical columns (NAND string) 452.

FIG. 4F depicts a cross sectional view of region 429 of FIG. 4C that includes a portion of vertical column 472. In one embodiment, the vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, vertical column 472 includes an inner core layer 490 that is made of a dielectric, such as SiO₂. Other materials can also be used. Surrounding inner core 490 is polysilicon channel 491. Materials other than polysilicon can also be used. Note that it is the channel 491 that connects to the bit line and the source line. Surrounding channel 491 is a tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is charge trapping layer 493, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

FIG. 4F depicts dielectric layers DL239, DL240, DL241, DL242 and DL243, as well as word line layers WL234, WL235, WL236, WL237, and WL238. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer 493. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel 491, tunneling dielectric 492, charge trapping layer 493, blocking oxide layer 498, aluminum oxide layer 497 and word line region 496. For example, word line layer WL238 and a portion of vertical column 472 comprise a memory cell MC1. Word line layer WL237 and a portion of vertical column 472 comprise a memory cell MC2. Word line layer WL236 and a portion of vertical column 472 comprise a memory cell MC3. Word line layer WL235 and a portion of vertical column 472 comprise a memory cell MC4. Word line layer WL234 and a portion of vertical column 472 comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 493 which is associated with (e.g. in) the memory cell. These electrons are drawn into the charge trapping layer 493 from the channel 491, through the tunneling dielectric 492, in response to an appropriate voltage on word line region 496. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

FIG. 4G is a schematic diagram of a portion of the memory array 202 depicted in in FIGS. 4-4F. FIG. 4G shows physical data word lines WL0-WL239 running across the entire block. The structure of FIG. 4G corresponds to a portion 406 in Block 2 of FIG. 4A, including bit line 411. Within the block, in one embodiment, each bit line is connected to five NAND strings. Thus, FIG. 4G shows bit line connected to NAND string NS0 (which corresponds to vertical column 436), NAND string NS1 (which corresponds to vertical column 446), NAND string NS2 (which corresponds to vertical column 456), NAND string NS3 (which corresponds to vertical column 466), and NAND string NS4 (which corresponds to vertical column 476). As mentioned above, in one embodiment, SGD0, SGD1 and SGD2 are connected together to operate as a single logical select gate for each sub-block separated by isolation regions (482, 484, 486 and 486) to form SGD-s 0, SGD-s 1, SGD-s 2, SGD-s 3, and SGD-s 4. SGS0, SG1 and SGS2 are also connected together to operate as a single logical select gate that is represented in FIG. 4G as SGS. Although the select gates SGD-s 0, SGD-s 1, SGD-s 2, SGD-s 3, and SGD-s 4 are isolated from each other due to the isolation regions, the data word lines WL0-WL239 of each sub-block are connected together.

The isolation regions (482, 484, 486 and 486) are used to allow for separate control of sub-blocks. A first sub-block corresponds to those vertical NAND strings controlled by SGD-s 0. A second sub-block corresponds to those vertical NAND strings controlled by SGD-s 1. A third sub-block corresponds to those vertical NAND strings controlled by SGD-s 2. A fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s 3. A fifth sub-block corresponds to those vertical NAND strings controlled by SGD-s 4.

FIG. 4G only shows NAND strings connected to bit line 411. However, a full schematic of the block would show every bit line and five vertical NAND strings (that are in separate sub-blocks) connected to each bit line.

Although the example memories of FIGS. 4-4G are three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein.

The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 5A is a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell data are referred to as single level cells (“SLC”). The data stored in SLC memory cells is referred to as SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data. FIG. 5A shows two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells that have threshold voltages in threshold voltage distribution E are, therefore, in the erased data state (e.g., they are erased). Memory cells that have threshold voltages in threshold voltage distribution P are, therefore, in the programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.” FIG. 5A depicts read reference voltage Vr. By testing (e.g., performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine a memory cells is erased (state E) or programmed (state P). FIG. 5A also depicts verify reference voltage Vv. In some embodiments, when programming memory cells to data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv.

FIGS. 5B-D illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). The data stored in MLC memory cells is referred to as MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In the example embodiment of FIG. 5B, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, or five bits of data per memory cell).

FIG. 5B shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B and C for programmed memory cells are also depicted. In one embodiment, the threshold voltages in the distribution E are negative and the threshold voltages in distributions A, B and C are positive. Each distinct threshold voltage distribution of FIG. 5B corresponds to predetermined values for the set of data bits. In one embodiment, each bit of data of the two bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all bits of data stored in a memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 1 provides an example encoding scheme.

TABLE 1 E A B C LP 1 0 0 1 UP 1 1 0 0

In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state E directly to any of the programmed data states A, B or C using the process of FIG. 6 (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program memory cells directly into data states A, B, and/or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and/or from data state E to data state C. The arrows of FIG. 5B represent the full sequence programming. In some embodiments, data states A-C can overlap, with memory controller 120 (or control die 211) relying on error correction to identify the correct data being stored.

FIG. 5C depicts example threshold voltage distributions for memory cells where each memory cell stores three bits of data per memory cells (which is another example of MLC data). FIG. 5C shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A - G represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for embodiments in which each bit of data of the three bits of data stored in a memory cell are in different pages, referred to as a lower page (LP), middle page (MP) and an upper page (UP).

TABLE 2 Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

FIG. 5C shows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, ...) a memory cell is in.

FIG. 5C also shows seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether the memory cells have threshold voltages greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have their threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG. FIG. 5C also shows Vev, which is a voltage level to test whether a memory cell has been properly erased.

In an embodiment that utilizes full sequence programming, memory cells can be programmed from the erased data state Er directly to any of the programmed data states A-G using the process of FIG. 6 (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and/or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and/or from data state Er to data state C, and so on. The arrows of FIG. 5C represent the full sequence programming. In some embodiments, data states A-G can overlap, with control die 211 and/or memory controller 120 relying on error correction to identify the correct data being stored. Note that in some embodiments, rather than using full sequence programming, the system can use multi-pass programming processes known in the art.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG, of FIG. 5C) or verify operation (e.g. see verify target levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG of FIG. 5C) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

FIG. 5D depicts threshold voltage distributions when each memory cell stores four bits of data, which is another example of MLC data. FIG. 5D depicts that there may be some overlap between the threshold voltage distributions (data states) S0 - S15. The overlap may occur due to factors such as memory cells losing charge (and hence dropping in threshold voltage). Program disturb can unintentionally increase the threshold voltage of a memory cell. Likewise, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the locations of the threshold voltage distributions may change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltages can help to mitigate such effects. Using ECC during the read process can fix errors and ambiguities. Note that in some embodiments, the threshold voltage distributions for a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other. The threshold voltage distributions of FIG. 5D will include read reference voltages and verify reference voltages, as discussed above.

When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above, or multi-pass programming processes known in the art. Each threshold voltage distribution (data state) of FIG. 5D corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 3 provides an example of an encoding scheme for embodiments in which each bit of data of the four bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP), an upper page (UP) and top page (TP).

TABLE 3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

FIG. 6 is a flowchart describing one embodiment of a process for programming memory cells. For purposes of this document, the term program and programming are synonymous with write and writing. In one example embodiment, the process of FIG. 6 is performed for memory array 202 using the one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) discussed above. In one example embodiment, the process of FIG. 6 is performed by integrated memory assembly 207 using the one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) of control die 211 to program memory cells on memory die 201. The process includes multiple loops, each of which includes a program phase and a verify phase. The process of FIG. 6 is performed to implement the full sequence programming, as well as other programming schemes including multi-stage programming. When implementing multi-stage programming, the process of FIG. 6 is used to implement any/each stage of the multi-stage programming process.

Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of FIG. 6 , the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ~12-16 V or another suitable level) and a program counter PC maintained by state machine 262 is initialized at 1. In one embodiment, the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step 604 the control die will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step 606, NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ~7-11 volts) to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string.

In step 608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage. In step 608, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming.

In step 610, program verify is performed and memory cells that have reached their target states are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step 610, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state.

If, in step 612, it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 614. Otherwise if, in step 612, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 616.

In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution are counted. That is, the number of memory cells that have, so far, failed to reach their target state are counted. This counting can be done by state machine 262, memory controller 120, or another circuit. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.

In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a status of “PASS” is reported in step 614. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), then the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.

If the number of failed memory cells is not less than the predetermined limit, then the programming process continues at step 620 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 624. If the program counter PC is less than the program limit value PL, then the process continues at step 626 during which time the Program Counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1 - 1.0 volts). After step 626, the process loops back to step 604 and another program pulse is applied to the selected word line (by the control die) so that another iteration (steps 604-626) of the programming process of FIG. 6 is performed.

In one embodiment memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from state P to state E of FIG. 5A, from states A/B/C to state E of FIG. 5B, from states A-G to state Er of FIG. 5C or from states S1-S15 to state S0 of FIG. 5D.

One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage (e.g., a low voltage) is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the non-volatile storage elements (memory cells). Herein, this is referred to as p-well erase.

Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the NAND string channel potential to erase the memory cells. Herein, this is referred to as GIDL erase. Both p-well erase and GIDL erase may be used to lower the threshold voltage (Vt) of memory cells.

In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a select transistor (e.g., SGD and/or SGS). A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers, e.g., holes, predominantly moving into NAND channel, thereby raising potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of memory cells and recombine with electrons there, to lower the threshold voltage of the memory cells.

The GIDL current may be generated at either end of the NAND string. A first GIDL voltage may be created between two terminals of a select transistor (e.g., drain side select transistor - SGD) that is connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a select transistor (e.g., source side select transistor - SGS) that is connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase.

As discussed above, in order to insure that non-volatile memory stores data reliably, non-volatile memory is tested during the development phase and during the manufacturing phase. FIG. 7 is a block diagram depicting the testing of non-volatile memory, and shows an integrated circuit tester 704 connected to a personal computer 702 and a memory die assembly 706. For purposes of this document, a memory die assembly includes one or more die directly connected to each other that includes one or more non-volatile memory arrays (or other non-volatile memory structures) and the peripheral circuits (e.g., 220, 230, 260) used to operate the one or more non-volatile memory arrays. Memory die assembly 706 is separate from and configured to communicate with memory controller 120. Memory die 200 of FIG. 2A is one embodiment of a memory die assembly 180. Integrated memory assembly 207 of FIG. 2B is another embodiment of a memory die assembly 180.

Memory die assembly (which is separate from and different than memory controller 120) is configured to connect to and communicate with memory controller 120 when installed in a storage system and being used in the field by a user. However, FIG. 7 shows memory die assembly 706 not connected to memory controller 120, as memory die assembly 706 is connected to integrated circuit tester 704 for purposes of testing prior to connection of memory die assembly 706 to memory controller 120.

In one embodiment, integrated circuit tester 704 creates test patterns, sends those test patterns to memory die assembly 706, sends multiple commands to memory die assembly 706 to perform multiple tests (some of the tests use the test pattems), receives multiple results for the multiple tests, and repeats all of the above steps for thousands of cycles. Computer 702 (laptop, desktop, server, smartphone, etc.) controls integrated circuit tester 704, including sending commands (and, in some cases, test patterns) to integrated circuit tester 704 and receiving result data for each or a subset of the cycles of tests. In the above scenarios, each test of each cycle is performed by memory die assembly 706 in response to a set of one or more commands, and results in a set of one or more responses. Therefore, to preform tens of thousands of cycles, a lot of time is used for communicating between computer 702, integrated circuit tester 704 and memory die assembly 706. In some instances, the amount of time for operating integrated circuit tester 704 and for communicating between computer 702, integrated circuit tester 704 and memory die assembly 706 can utilize up to 80% of the testing time. Therefore, the testing time can be reduced by reducing the amount of time operating integrated circuit tester 704 and for communicating between computer 702, integrated circuit tester 704 and memory die assembly 706. This is accomplished by including within memory die assembly 706 the ability to automatously test itself in response to a command from integrated circuit tester 704.

FIG. 8 is a flow chart describing one embodiment of a process for autonomous testing of a memory die assembly. The process of FIG. 8 can be performed by any one of the one or more control circuits discussed above connected to one or more memory arrays (or other memory structures) as discussed above. For example, the process of FIG. 8 can be performed by and/or at the direction of ACM 269 (which is part of the one or more control circuits discussed above). In one embodiment, ACM 269 is built into state machine 262 or another processor in the memory die assembly. The process of FIG. 8 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 8 is performed by or at the direction of state machine 262 and/or ACM 269, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. The process of FIG. 8 can be used for the embodiment of FIG. 7 , with integrated circuit tester 704 connected to personal computer 702 and memory die assembly 706, such that memory die assembly 706 is the device under test that is performing the autonomous testing by running a group of tests multiple times, where each time the group of tests is run is referred to as a cycle. In one embodiment, the group of tests include erasing, programming and reading memory cells of the memory die assembly 706.

In one embodiment, the process of FIG. 8 is performed on a non-volatile storage apparatus comprising a non-volatile memory structure that includes multiple planes of non-volatile memory cells and one or more control circuits connected to the non-volatile memory structure to form a memory die assembly. In step 802 of FIG. 8 , the one or more control circuits (e.g., ACM 269) of the memory die assembly receives a request from outside the memory die assembly (e.g., from integrated circuit tester 704) to perform autonomous testing of the memory die assembly (e.g., many cycles of a group of tests). In step 804, in response to the request received in step 802, the one or more control circuits (e.g., ACM 269) of the memory die assembly repeatedly perform a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure. In step 806, the one or more control circuits record failure events from the tests by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event, a type of test that failed, and a cycle during which the failure event occurred. More details of steps 804 and 806 are provided below.

A failure event is an occurrence of a test that is not completed successfully. For example, if the group of tests includes programming and the programming of word line X of block Y fails, that is an example of a failure event. As another example, if a page of data sensed during a reading test cannot be successfully decoded then a failure event has occurred for that page. If a block is being erased, and all (or a sufficient number) of the memory cells cannot be moved to the erased data state within a predetermined amount of time, then a failure event has occurred for that block. Other failure events can also be generated.

FIG. 9 is a flow chart describing another embodiment of a process for autonomous testing of a memory die assembly. The process of FIG. 9 can be performed by any one of the one or more control circuits discussed above connected to one or more memory arrays (or other memory structures) as discussed above. For example, the process of FIG. 9 can be performed by and/or at the direction of ACM 269 (which is part of the one or more control circuits discussed above). The process of FIG. 9 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 9 is performed by or at the direction of state machine 262 and/or ACM 269, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. The process of FIG. 9 can be used for the embodiment of FIG. 7 , with integrated circuit tester 704 connected to personal computer 702 and memory die assembly 706, such that memory die assembly 706 is the device under test that is performing the autonomous testing by running a group of tests multiple times, where each time the group of tests is run is referred to as a cycle. In one embodiment, the group of tests include erasing, programming and reading memory cells of the memory die assembly 706. The process of FIG. 9 is an example implementation of the process of FIG. 8 .

In one embodiment, the process of FIG. 9 is performed on a non-volatile storage apparatus comprising a non-volatile memory structure that includes multiple planes of non-volatile memory cells; temporary data storage (e.g., DRAM, SRAM, registers, etc.) divided into portions such that each portion is associated with one of the planes; and one or more control circuits connected to the non-volatile memory structure and the temporary storage to form a memory die assembly. In step 902 of FIG. 9 , the one or more control circuits (e.g., ACM 269) of the memory die assembly receive a request from outside a memory die assembly (e.g., integrated circuit tester 704) to perform autonomous testing of the memory die assembly. In response to the request received in step 902, the one or more control circuits (e.g., ACM 269) of the memory die assembly perform multiple cycles of autonomous testing on the memory die assembly. Each cycle of the autonomous testing includes testing each of the multiple planes by performing a first test (e.g., at least one of erasing, programming or reading memory cells) multiple times. Each time the first test is performed, the first test is performed on a subset of the planes and error data for failure events from the first test is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes. The planes in the subset of planes change over the multiple times the test is performed. More details of step 904 are described below, including with respect to FIGS. 14A-C and 15A1/15A2. In step 906 of FIG. 9 , the one or more control circuits move the data for the failure events from the temporary data storage to the non-volatile memory structure.

Step 904 of FIG. 9 includes storing error data in temporary data storage. While it is possible to create a new memory in the memory die assembly to store the error data, an additional new memory added to the memory die assembly would increase the size of the memory die assembly. Therefore, it is proposed to use already existing temporary storage in a manner that does not interfere with operation of the memory die assembly. In one set of embodiments, the temporary data storage comprises the XDL latches, which are implemented as part of cache buffer 405 (see FIG. 4A1 ). As discussed above with respect to FIG. 4A1 , under each plane is a separate portion of the cache buffer associated with the plane that the portion of the cache buffer is underneath. That is, in one embodiment, the temporary data storage is the set of XDL latches implemented as a cache buffer, and each portion of the cache buffer is under a plane of memory cells. Each time the first test is performed (step 904), it is performed on less than all planes so that one plane is not being tested and the error data will be stored in the XDL latches (the portion of the cache buffer) beneath the plane not being tested (also known as the free plane). For example, in one instance blocks of Plane 0, Plane 1 and Plane 2 may be concurrently erased as part of a test for erasing, and any error data for failure events from the test for erasing blocks of Plane 0, Plane 1 and Plane 2 is recorded in the XDL latches (the portion of the cache buffer) beneath the Plane 3 (the free plane). Each time the test is performed, the subset of planes under test will change, therefore, the free plane will also change. In the above example, Plane 0, Plane 1 and Plane 2 were under test while Plane 3 was the free plane; however, in a next test Plane 3, Plane 0 and Plane 1 will be under test while Plane 2 will be the free plane. This concept of rotating the planes under test and choosing where to store error data for failure events is explained, for at least one set of embodiments, with respect to FIGS. 10 and 11 .

FIG. 10 is a block diagram depicting the ganging of blocks and saving of error data from the autonomous testing of a memory die assembly. In the embodiment of FIG. 4A, the memory die assembly includes four planes: Plane 0, Plane 1, Plane 2 and Plane 3. Each time a test is performed during a cycle of the autonomous testing, the test is performed on three planes. Therefore, each time a test is performed during a cycle of the autonomous testing three planes need to be chosen for test. The portions of the three planes chosen for test are ganged together to be tested concurrently. FIG. 10 shows three blocks (Block N, Block N+1, Block N+2) ganged together to be tested concurrently for the same test. In this embodiment (see FIG. 4A), Block N is in a first plane, Block N+1 is in a second plane, and Block N+2 is in a third plane. Block N+3, not selected yet for test, is in a fourth plane. When testing Block N, Block N+1 and Block N+2, error data for failure events is stored in the portion of XDL that is underneath (and, thereby, associated with) the fourth plane (which includes Block N+3).

For example (see FIG. 4A), Block 4 (N=4) is in Plane 0, Block 5 is in Plane 1, Block 6 is in Plane 2 and Block 7 is in Plane 3. If the test being performed is to erase the blocks, then when performing the erase test on Block 4, Block 5 and Block 6, error data for failure events is stored in the portion of XDL that is underneath (and, thereby, associated with) the Plane 3 (which includes Block 7). The next time the erase test is performed, the blocks under test will be Block 7, Block 8 and Block 9 with error data for failure events being stored in the portion of XDL that is underneath (and, thereby, associated with) the Plane 2 (which includes Block 10). Note that in other embodiments, the number of planes under test can be different than three planes and the planes under test need not be tested concurrently. Initially saving the error data in the temporary storage (e.g. XDL) saves time during the test. The error data is later moved to non-volatile storage for long term storage and access by the integrated circuit tester 704 and computer 702.

FIG. 11 is a table that provides one example of ganging blocks and shows where error data is stored during the autonomous testing. Each row is one performance of the test. The first time the test is performed, Blocks 0-2 are tested and error data for failure events is stored in the portion of XDL that is underneath (and, thereby, associated with) the Plane 3 (which includes Block 3). The second time the test is performed, Blocks 3-5 are tested and error data for failure events is stored in the portion of XDL that is underneath (and, thereby, associated with) the Plane 2 (which includes Block 6). The third time the test is performed, Blocks 6-8 are tested and error data for failure events is stored in the portion of XDL that is underneath (and, thereby, associated with) the Plane 1 (which includes Block 9), and so on. The rotating of the blocks under test and the target of the error data depicted in FIGS. 10 and 11 may be used with the processes of FIGS. 8 and/or 9 .

The discussion above with respect to FIGS. 10 and 11 describe which portion of the set of XDL latches (e.g., cache buffer 405) to store the error data for failure events. However, the storage of the error data for failure events is only temporary and, in step 906 of FIG. 9 , the error data for failure events is moved from XDL to the non-volatile memory 202 for long term storage. After all of the cycles of testing have completed, the memory die assembly 706 will notify the integrated circuit tester 704 that the testing is complete. The integrated circuit tester 704 can then access all of the error data for failure events from the non-volatile memory 202 for reporting to computer 702.

Each time a failure event occurs, a record of error data for the failure event is stored in XDL (and later moved to the non-volatile memory). FIG. 12 is a table depicting one embodiment of a format for the record of error data. In one embodiment, each record includes six bytes (Byte 0, Byte 1, Byte 2, Byte 3, Byte 4 and Byte 5). Bytes 0-2, and one bit of Byte 3, store an address of where (plane, block, sub-block, word line and page) in the non-volatile memory 202 the failure event occurred. Bytes 3 and 4, and two bits of Byte 5, indicate the cycle number during which the failure event occurred. Bits 2 and 3 of Byte 5 indicates the type of failure (e.g., erase failure, program failure, no delay read failure and delay read failure).

As mentioned above, step 906 of FIG. 9 includes moving the records of error data for failure events from XDL to the non-volatile memory 202. FIG. 13 is a block diagram depicting how the records of FIG. 12 are stored in non-volatile memory 202. When a record of error data for a failure event is stored in non-volatile memory 202, it is stored as four copies of SLC data including two regular copies (e.g., R0C0 and R0C1) and two inverted copies (e.g., ~R0C0 and ~R0C1) for fault tolerance purposes. Note that in one embodiment, an inverted copy has all bits flipped as compared to a regular copy. FIG. 13 shows one page of data. In one embodiment, a page of data is 16 K Bytes. Therefore, records for 682 failure events can be stored in one page of data (e.g., 16 K/(4*6)≈682).

FIGS. 14A-C together form a flow chart describing another embodiment of a process for autonomous testing of a memory die assembly. The process of FIGS. 14A-C can be performed by any one of the one or more control circuits discussed above connected to one or more memory arrays (or other memory structures) as discussed above. For example, the process of FIGS. 14A-C can be performed by and/or at the direction of ACM 269 (which is part of the one or more control circuits discussed above). The process of FIGS. 14A-C can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIGS. 14A-C is performed by or at the direction of state machine 262 and/or ACM 269, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. The process of FIGS. 14A-C can be used for the embodiment of FIG. 7 , with integrated circuit tester 704 connected to personal computer 702 and memory die assembly 706, such that memory die assembly 706 is the device under test that is performing the autonomous testing by running a group of tests multiple times, where each time the group of tests is run is referred to as a cycle. In one embodiment, the group of tests include erasing, programming and reading memory cells of the memory die assembly 706. The process of FIGS. 14A-C is an example implementation of the process of FIG. 8 and/or the process of FIG. 9 , using the teachings of FIGS. 10-13 .

In step 1402 of FIG. 14A, the one or more control circuits (e.g., ACM 269) of the memory die assembly receives a request from outside the memory die assembly (e.g., from integrated circuit tester 704 or other entity) to perform autonomous testing of the memory die assembly (e.g., many cycles of a group of tests). In step 1404, the block number is initialized (N=0) to the first set of blocks Block N = Block 0, Block N+1 = Block 1 and Block N+2 = Block 2 (e.g., as per table of FIG. 11 ). In step 1406, Block N, Block N+1 and Block N+2 are ganged together so that they are tested together (e.g., as per FIGS. 10 and 11 ). In step 1408, the ganged blocks (Block N, Block N+1 and Block N+2) are erased. In one embodiment, Block N, Block N+1 and Block N+2 are erased concurrently. In another embodiment, Block N, Block N+1 and Block N+2 are erased serially. The erase process used in step 1408 can be a standard erase process known in the art to move the memory cells of Block N, Block N+1 and Block N+2 to the erased data state (e.g., Er of FIG. 5C). As part of the erase process, the one or more control circuits determine if the erase process completed successfully. For example, it is determined whether all (or a sufficient number) of memory cells have their threshold voltage lower than Vev (see FIG. 5C). If so, the one or more control circuits return a status of “pass.” If the one or more control circuits determine that not all (or not a sufficient number) of memory cells have their threshold voltage lower than Vev, then the one or more control circuits return a status of “fail.” The status can be stored in a register, a location in volatile memory or a location in the non-volatile memory 202. If the status is “fail” (step 1410) then there is a failure event, as the erase process failed, and the process continues at step 1486 in order to record the error data for the failure event. If the status is “pass” (step 1410) then it is determined in step 1412 whether the last block of the memory die assembly was erased. That is, has the erase test been performed on all blocks that it needs to be performed? If so, then the testing process of FIGS. 14A-C continues at step 1420 to start the next test.

If there are still more blocks to erase (step 1412), then the testing process of FIGS. 14A-C continues at step 1414 to prepare to erase a new set of ganged blocks. Because a new set of ganged blocks will be operated on, the error data needs to be moved to a new portion of XDL. In one embodiment, the error data is transferred from XDL of Plane ((N+3)MOD4) to XDL of Plane ((N+2)MOD4). For example, the first time the erasing is performed is for Block 0, Block 1 and Block 2, with error data being stored in XDL for Plane 3 (associated with Block 3); and the second time the erasing is performed is for Block 3, Block 4 and Block 5, were error data being stored in XDL for Plane 2 (associated with Block 6), as depicted in FIG. 11 . Therefore, in this example the error data is moved from XDL for Plane 3 (e.g., [0+3]MOD4 = 3) to XDL for Plane 2 (e.g., [0+2]MOD4 = 2). After transferring the error data in step 1414, N is increased by three (N=N+3) in step 1416 and the process loops back to step 1406 in order to gang the next three blocks and then erase those ganged blocks.

If, in step 1412, it was determined that there are no more blocks that need to be erased, then the testing process of FIGS. 14A-C continues at step 1420 to perform the next test, which (in this example embodiment) includes programming. In step 1420, the block number is initialized (N=0) to the first set of blocks Block N = Block 0, Block N+1 = Block 1 and Block N+2 = Block 2. In step 1422, Block N, Block N+1 and Block N+2 are ganged together so that they are tested together (e.g., as per FIGS. 10 and 11 ). The test programs data into one word line at a time for each block under test. Thus, in step 1424, one word line from each of blocks N, N+1 and N+2 are ganged together to be programmed together (e.g., concurrently). In step 1426, the one or more control circuits concurrently program a random data pattern (created by the one or more control circuits inside the memory die assembly) into the ganged word lines from blocks N, N+1 and N+2.

As part of the program process, the one or more control circuits determine if the program process completed successfully. For example, it is determined whether all (or a sufficient number) of memory cells have their threshold voltage greater than corresponding verify reference voltages (e.g., VvA, VvB, VvC, VvD, VvE, VvF, and VvG of FIG. 5C). If so, the one or more control circuits return a status of “pass.” If the one or more control circuits determine that not all (or not a sufficient number) of memory cells have their threshold voltage greater than corresponding verify reference voltages, then the one or more control circuits return a status of “fail.” The status can be stored in a register, volatile memory or non-volatile memory 202. If the status is “fail” (step 1428) then there is a failure event, as the programming process failed, and the process continues at step 1486 in order to record the error data for the failure event. If the status is “pass” (step 1428), then it is determined in step 1430 whether the last word line of the ganged blocks being tested was just programmed. If not, then the next word line is chosen in each of blocks N, N+1 and N+2 and the process loops back to step 1424 to gang and program the next word line for each of the three bocks under test. If, in step 1430, it is determined that the last word line of the ganged blocks being tested was just programmed, then all word lines for blocks N, N+1 and N+2 have been programmed/tested (for this cycle) and in step 1434 it is determined whether the last block was just programmed/tested (i.e. have all blocks have been programmed/tested).

If the last block was not just programmed/tested (i.e. more blocks need to be programmed/tested), then the testing process of FIGS. 14A-C continues at step 1436 to prepare to program a new set of ganged blocks. Because a new set of ganged blocks will be operated on, the error data needs to be moved to a new portion of XDL. In one embodiment, the error data is transferred from XDL of Plane ((N+3)MOD4) to XDL of Plane ((N+2)MOD4). After transferring the error data in step 1436, N is increased by three (N=N+3) in step 1438 in order to choose the next three blocks and the process loops back to step 1422 in order to gang the next three blocks and then program those ganged blocks.

If the last block was just programmed/tested (step 1434), then the programming test has been performed on all blocks that it needs to be performed; therefore, the testing process of FIGS. 14A-C continues at step 1450 to start the next test (see FIG. 14B), which includes reading. In other embodiments other tests and other orders of the tests can also be implemented. In step 1450, the block number is initialized (N=0) to the first set of blocks Block N = Block 0, Block N+1 = Block 1 and Block N+2 = Block 2. In step 1452, Block N, Block N+1 and Block N+2 are ganged together so that they are tested together (e.g., as per FIGS. 10 and 11 ). The reading test reads data from one page at a time for each block under test. Thus, in step 1454, one page from each of blocks N, N+1 and N+2 are ganged together to be read together (e.g., concurrently). In step 1456, the one or more control circuits concurrently read the pages of data from blocks N, N+1 and N+2.

As part of the read process, the one or more control circuits determine if the read process completed successfully. For example, it is determined whether the data sensed can be successfully decoded. If so, the one or more control circuits return a status of “pass.” If the one or more control circuits determine that the data sensed cannot be successfully decoded, then the one or more control circuits return a status of “fail.” The status can be stored in a register, volatile memory or non-volatile memory 202. If the status is “fail” (step 1458) then there is a failure event, as the read process failed, and the process continues at step 1486 in order to record the error data for the failure event. If the status is “pass” (step 1458) then it is determined in step 1460 whether the last page of the ganged blocks being tested was just read. If not, then the next page is chosen in each of blocks N, N+1 and N+2 (step 1462) and the process loops back to step 1454 to gang and read the next pages for the three bocks under test. If, in step 1460, it is determined that the last page of the ganged blocks being tested was just read, then all pages for blocks N, N+1 and N+2 have been read/tested (for this cycle) and in step 1466 the block status is updated to be a good block.

In step 1468, it is determined whether the last block was just read/tested (i.e. have all blocks have been read/tested). If the last block was not just read/tested (i.e. more blocks need to be read/tested), then the testing process of FIGS. 14A-C continues at step 1470 to prepare to read a new set of ganged blocks. Because a new set of ganged blocks will be operated on, the error data needs to be moved to a new portion of XDL. In one embodiment, the error data is transferred from XDL of Plane ((N+3)MOD4) to XDL of Plane ((N+2)MOD4). After transferring the error data in step 1470, N is increased by three (N=N+3) in step 1472 in order to choose the next three blocks and the process loops back to step 1452 in order to gang the next three blocks and then read from those ganged blocks.

If the last block was just read/tested (step 1468), then the read test has been performed on all blocks that it needs to be performed; therefore, the testing process of FIGS. 14A-C has completed one cycle of testing (e.g., steps 1404-1468 are one cycle). In step 1476, it is determined whether the memory assembly needs to perform additional cycles of testing. If the last cycle was just performed, then no more cycles need to be performed and in step 1480 the one or more control circuits returns a status for the autonomous test. For example, the one or more control circuits of the memory die assembly 706 may inform the integrated circuit tester 704 that the autonomous test has completed. In some embodiments, when the integrated circuit tester 704 sends a request to memory die assembly 706 to perform the autonomous test (see step 1402), that request indicates how many cycles to perform. In another embodiment, integrated circuit tester 704 sends a separate command to memory die assembly 706 indicating how many cycles to perform. Alternatively, memory die assembly 706 is preprogrammed to with an indication of how many cycles to perform.

If, in step 1476, it is determined that cycle of testing was not the last cycle (i.e. there are more cycles to perform), then the cycle count is increased in step 1478 and the process loops back to step 1404 to start the next cycle of testing.

As mentioned above, if the status for any of the tests is “fail” (see steps 1410, 1428 and 1458) then there is a failure event and the process continues at step 1486 (FIG. 14C) in order to record the error data for the failure event. The error data is stored in a record (see FIG. 12 ) in a portion of XDL associated with Plane (N+3)MOD4. For example, if N=6 and the tests are being performed on blocks 6, 7 and 8, then the error data is stored in a record in a portion of XDL associated with Plane 1 (e.g., 6+3MOD4=1). In step 1488, the one or more control circuits determine whether the error data stored in the portion of XDL associated with Plane (N+3)MOD4 is equal to or greater than 4K bytes. If so, then the data needs to be flushed to the non-volatile memory as the page of data in non-volatile memory is 16K bytes, the error data is stored as four copies (2 regular copies and 2 inverted copies), and four copies of the 4K bytes of error data in XDL use the full page of 16K bytes in non-volatile memory. Therefore, in step 1488, the one or more control circuits program the error data stored in the portion of XDL associated with Plane (N+3)MOD4 as two regular copies and two inverted copies into the non-volatile memory 202, as depicted in FIG. 13 . In other embodiments, more or less than two regular copies and two inverted copies can be programmed (multiple copies can be programmed) into the non-volatile memory. In one embodiment, one or more blocks of non-volatile memory array 202 can be reserved for storing the error data. After the programming of the error data into non-volatile memory, the portion of XDL used to store that error data can be free to store new error (or other) data, and the process of FIGS. 14A-C resumes (step 1492). For example, if during the test for erasing (see step 1408) of Block 12 results in a failure event, then in step 1486 error data is stored in the portion of XDL associated with Plane 3 and, as per step 1492, the process resumes at step 1412 where it is determined that more blocks need to be erased so the process continues to step 1414 and step 1416 in order to choose blocks 15, 16 and 17 for the next erase test in step 1408.

If in step 1488, it is determined that the error data stored in the portion of XDL associated with Plane (N+3)MOD4 is less than 4K bytes, then it is determined whether the failure event just processed in step 1486 is the last failure event for the autonomous testing (step 1494). If so, then the process continues at step 1490. If not, then the process continues at step 1492.

FIGS. 15A1, 15A2, 14B and 14C together form a flow chart describing another embodiment of a process for autonomous testing of a memory die assembly. The process of FIGS. 15A1, 15A2, 14B and 14C can be performed by any one of the one or more control circuits discussed above connected to one or more memory arrays (or other memory structures) as discussed above. For example, the process of FIGS. 15A1, 15A2, 14B and 14C can be performed by and/or at the direction of ACM 269 (which is part of the one or more control circuits discussed above). The process of FIGS. 15A1, 15A2, 14B and 14C can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIGS. 15A1, 15A2, 14B and 14C is performed by or at the direction of state machine 262 and/or ACM 269, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. The process of FIGS. 15A1, 15A2, 14B and 14C can be used for the embodiment of FIG. 7 , with integrated circuit tester 704 connected to personal computer 702 and memory die assembly 706, such that memory die assembly 706 is the device under test that is performing the autonomous testing by running a group of tests multiple times, where each time the group of tests is run is referred to as a cycle. In one embodiment, the group of tests include erasing, programming and reading memory cells of the memory die assembly 706. The process of FIGS. 15A1, 15A2, 14B and 14C is an example implementation of the process of FIG. 8 and/or the process of FIG. 9 , using the teachings of FIGS. 10-13 . One difference between the process of FIGS. 14A-C and the process of 15A1, 15A2, 14B and 14C is that the process of 15A1, 15A2, 14B and 14C performs a first read test with the programming test, and then performs a separate second read test after the programming test has been completed.

Steps 1402 - 1430 of FIG. 15A1 are performed in the same manner as described above fir FIG. 14A. However, if in step 1430 of FIG. 15A1 it is determined that the last word line of the ganged blocks being tested was just programmed, then all word lines for blocks N, N+1 and N+2 have been programmed/tested (for this cycle) and the process continues at step 1500 of FIG. 15A2 to perform the first read test for blocks N, N+1 and N+2. In step 1500, the one or more control circuits gang pages of blocks N, N+1 and N+2 (e.g., one page from each of the three blocks) and in step 1502 the one or more control circuits read the data stored in the ganged pages of blocks N, N+1 and N+2. If the status of the read process of step 1502 is “fail” (step 1504) then there is a failure event, as the read process failed, and the process continues at step 1486 of FIG. 14C in order to record the error data for the failure event. If the status is “pass” (step 1504) then it is determined in step 1506 whether the last page of the ganged blocks being tested was just read. If not, then the next page is chosen in each of blocks N, N+1 and N+2 (step 1508) and the process loops back to step 1500 to gang and read the next pages for the three bocks under test. If, in step 1506, it is determined that the last page of the ganged blocks being tested was just read, then all pages for blocks N, N+1 and N+2 have been read/tested (for this cycle) and in step 1510 it is determined whether the last block was just programmed and read (tested). If the last block was not just programmed and read (i.e. more blocks need to be programmed and read), then the testing process of FIGS. 15A1, 15A2, 14B and 14C continues at step 1512 to prepare to program a new set of ganged blocks. Because a new set of ganged blocks will be operated on, the error data needs to be moved to a new portion of XDL. In one embodiment, the error data is transferred from XDL of Plane ((N+3)MOD4) to XDL of Plane ((N+2)MOD4). After transferring the error data in step 1512, N is increased by three (N=N+3) in step 1514 in order to choose the next three blocks and the process loops back to step 1422 of FIG. 15A1 in order to gang the next three blocks and then program those ganged blocks.

If the last block was just programmed/tested (step 1510), then the programming/reading test has been performed on all blocks that it needs to be performed; therefore, the testing process of FIG. 15A1, 15A2, 14B and 14C continues at step 1450 of FIG. 14B to start the next test, which includes the second read test

A system has been described for autonomously testing a memory assembly by performing multiple cycles of a series of tests. By testing autonomously, the amount of time needed to test is reduced due to the reduction in messaging with an integrated circuit tester and due to the less amount of work performed by the integrated circuit tester.

One embodiment includes a non-volatile storage apparatus, comprising: a non-volatile memory structure; and one or more control circuits connected to the non-volatile memory structure to form a memory die assembly. The memory die assembly is separate from and configured to communicate with a memory controller. The one or more control circuits are configured to: receive a request from outside the memory die assembly (e.g., from an integrated circuit tester or a memory controller) to perform autonomous testing of the memory die assembly; in response to the request, repeatedly perform a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure; and record failure events from the tests by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event (e.g., memory cell, word line, block, plane, etc), a type of test that failed and a cycle during which the failure event occurred.

One embodiment includes a non-volatile storage apparatus, comprising: a non-volatile memory structure comprising multiple planes of non-volatile memory cells; temporary data storage divided into portions, each portion is associated with one of the planes; and one or more control circuits connected to the non-volatile memory structure and the temporary storage to form a memory die assembly. The memory die assembly is separate from and configured to communicate with a memory controller. The one or more control circuits are configured to perform a cycle of testing on the non-volatile memory structure. The cycle of testing includes testing each of the multiple planes by performing a first test multiple times such that each time the first test is performed of the multiple times the test is performed on a subset of the planes and error data for a failure event is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes. The planes in the subset of planes change over the multiple times the test is performed.

One embodiment includes a method of operating non-volatile storage, comprising: receiving a request from outside a memory die assembly to perform autonomous testing of the memory die assembly, the memory die assembly includes a non-volatile memory structure comprising multiple planes of non-volatile memory cells and temporary data storage divided into portions, each portion is associated with one of the planes; in response to the request, performing multiple cycles of autonomous testing on the memory die assembly, each cycle of the autonomous testing includes testing each of the multiple planes by performing a first test multiple times such that each time the first test is performed of the multiple times the test is performed on a subset of the planes and error data for failure events from the first test is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the test is performed; and moving the data for the failure events from the temporary data storage to the non-volatile memory structure.

For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “based at least in part on.”

For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. 

What is claimed is:
 1. A non-volatile storage apparatus, comprising: a non-volatile memory structure; and one or more control circuits connected to the non-volatile memory structure to form a memory die assembly, the memory die assembly is separate from and configured to communicate with a memory controller, the one or more control circuits are configured to: receive a request from outside the memory die assembly to perform autonomous testing of the memory die assembly; in response to the request, repeatedly perform a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure; and record failure events from the tests by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event, a type of test that failed and a cycle during which the failure event occurred.
 2. The non-volatile storage apparatus of claim 1, further comprising: temporary data storage comprising volatile memory positioned in the memory die assembly, the one or more control circuits are configured to first store the error data for each recorded failure event in the temporary data storage and subsequently move the error data for each recorded failure event to the non-volatile memory structure.
 3. The non-volatile storage apparatus of claim 1, further comprising: temporary data storage positioned in the memory die assembly, the non-volatile memory structure comprises multiple planes of non-volatile memory cells, the temporary data storage is divided into portions such that each portion is associated with one of the planes, for each cycle the one or more control circuits are configured to perform the group of tests for each of the multiple planes by performing a first test multiple times such that each time the first test is performed of the multiple times the first test is performed on a subset of the planes and error data for a failure event is stored in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the first test is performed.
 4. The non-volatile storage apparatus of claim 3, wherein: the one or more control circuits are configured to, after performing the first test on a first subset of the planes and storing first error data for a first failure event from the first test on the first subset of the planes in a portion of the temporary data storage associated with a first other plane not included in the first subset of the planes, move the first error data from the portion of the temporary data storage associated with the first other plane not included in the first subset of the planes to a portion of the temporary data storage associated with a second other plane not included in a second subset of the planes and perform the first test on the second subset of the planes and store second error data for a second failure event from the first test on the second subset of the planes in the portion of the temporary data storage associated with a second other plane.
 5. The non-volatile storage apparatus of claim 3, wherein: the one or more control circuits are configured to perform the first test on a subset of the planes by concurrently performing the first test on memory cells in a first plane, performing the first test on memory cells in a second plane, and performing the first test on memory cells in a third plane, and storing error data for a failure event in a portion of the temporary data storage associated with a fourth plane.
 6. The non-volatile storage apparatus of claim 3, wherein: the first test is a programming test; and each time the first test is performed of the multiple times a different randomly generated data pattern is used for programming.
 7. The non-volatile storage apparatus of claim 3, wherein: the one or more control circuits are configured to move the error data for failure events to the non-volatile memory structure from the temporary data storage.
 8. The non-volatile storage apparatus of claim 7, wherein: the one or more control circuits are configured to store multiple copies of the error data for failure events and multiple inverted copies of the error data for failure events in the non-volatile memory structure.
 9. The non-volatile storage apparatus of claim 3, wherein: the one or more control circuits are configured to move the error data for failure events to the non-volatile memory structure from the temporary data storage in response to an amount of the error data for failure events being greater than a threshold quantity.
 10. The non-volatile storage apparatus of claim 1, further comprising: temporary data storage positioned in the memory die assembly, the non-volatile memory structure comprises multiple planes of non-volatile memory cells, the temporary data storage is divided into portions such that each portion is associated with one of the planes; for each cycle the one or more control circuits are configured to perform the group of tests for each of the multiple planes by performing a first test, a second test and a third test multiple times; each time the first test is performed of the multiple times, the first test is performed on a subset of the planes and error data for a failure event during the first test is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the first test is performed; each time the second test is performed of the multiple times, the second test is performed on a subset of the planes and error data for a failure event is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the second test is performed; each time the third test is performed of the multiple times, the third test is performed on a subset of the planes and error data for a failure event is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the third test is performed.
 11. The non-volatile storage apparatus of claim 10, wherein: the first test is a programming test; the second test is a reading test; and the third test is an erase test.
 12. The non-volatile storage apparatus of claim 1, wherein: the non-volatile storage apparatus further comprises volatile temporary data storage positioned in the memory die assembly; the non-volatile memory structure comprises multiple planes, each plane includes multiple block of non-volatile memory cells, the volatile temporary data storage is divided into portions such that each portion is associated with one of the planes; for each cycle: the one or more control circuits are configured to perform the group of tests for each of the multiple planes by performing a first test multiple times such that each time the first test is performed of the multiple times the first test is performed concurrently on three blocks in three different planes with error data for a failure event being stored in a portion of the volatile temporary data storage associated with a fourth plane not included in the three different planes.
 13. The non-volatile storage apparatus of claim 1, wherein: the non-volatile memory structure are positioned on a first die; and the one or more control circuits are positioned on a second die that is directly bonded to the first die, the second die is configured to communicate with the memory controller, the memory die assembly includes the first die and the second die.
 14. The non-volatile storage apparatus of claim 1, further comprising: an integrated circuit tester connected to the one or more control circuits, the integrated circuit tester is configured to send the request to the one or more control circuits to perform autonomous testing of the memory die assembly.
 15. A non-volatile storage apparatus, comprising: a non-volatile memory structure comprising multiple planes of non-volatile memory cells; temporary data storage divided into portions, each portion is associated with one of the planes; and one or more control circuits connected to the non-volatile memory structure and the temporary storage to form a memory die assembly, the memory die assembly is separate from and configured to communicate with a memory controller, the one or more control circuits are configured to perform a cycle of testing on the non-volatile memory structure, the cycle of testing includes testing each of the multiple planes by performing a first test multiple times such that each time the first test is performed of the multiple times the test is performed on a subset of the planes and error data for a failure event is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the test is performed.
 16. The non-volatile storage apparatus of claim 15, wherein: the one or more control circuits are configured to, after performing the first test on a first subset of the planes and storing first error data for a first failure event from the first test on the first subset of the planes in a portion of the temporary data storage associated with a first other plane not included in the first subset of the planes, move the first error data from the portion of the temporary data storage associated with the first other plane not included in the first subset of the planes to a portion of the temporary data storage associated with a second other plane not included in a second subset of the planes and perform the first test on the second subset of the planes and store second error data for a second failure event from the first test on the second subset of the planes in the portion of the temporary data storage associated with a second other plane.
 17. The non-volatile storage apparatus of claim 15, wherein: the one or more control circuits are configured to move the error data for the failure event to the non-volatile memory structure from the temporary data storage.
 18. A method of operating non-volatile storage, comprising: receive a request from outside a memory die assembly to perform autonomous testing of the memory die assembly, the memory die assembly includes a non-volatile memory structure comprising multiple planes of non-volatile memory cells and temporary data storage divided into portions, each portion is associated with one of the planes; in response to the request, perform multiple cycles of autonomous testing on the memory die assembly, each cycle of the autonomous testing includes testing each of the multiple planes by performing a first test multiple times such that each time the first test is performed of the multiple times the test is performed on a subset of the planes and error data for failure events from the first test is recorded in a portion of the temporary data storage associated with a plane not included in the subset of the planes, the planes in the subset of planes change over the multiple times the test is performed; and move the data for the failure events from the temporary data storage to the non-volatile memory structure.
 19. The method of claim 18, wherein the testing each of the multiple planes by performing the first test multiple times comprises: performing the first test on a first subset of the planes and storing first error data for a first failure event from the first test on the first subset of the planes in a portion of the temporary data storage associated with a first other plane not included in the first subset of the planes; moving the first error data from the portion of the temporary data storage associated with the first other plane not included in the first subset of the planes to a portion of the temporary data storage associated with a second other plane not included in a second subset of the planes; and performing the first test on the second subset of the planes and storing second error data for a second failure event from the first test on the second subset of the planes in the portion of the temporary data storage associated with a second other plane.
 20. The method of claim 18, further comprising: sending the request to the memory die assembly to perform autonomous testing of the memory die assembly from an integrated circuit tester separate from and connected to the memory die assembly. 